摘要：
Top die pads are electrically relocated by forming holes through a semiconductor wafer between device active regions. An electrically insulating layer is formed over all exposed surfaces of the wafer, including within the holes, and openings are made in the insulating layer for access to the top interconnection pads. The wafer and holes are metallized and patterned to form bottom interconnection pads electrically connected to corresponding top interconnection pads by metallization extending within the holes. A dicing saw having a kerf width less than the diameter of the holes is employed to separate the individual devices. For accurate position alignment of repatterned die, an alignment structure, such as projecting pins or an egg crate structure, engages the die, and alignment pads can be patterned on the die.
权利要求：
What is claimed is:
1. A method for making an array of closely-spaced devices, said method comprising:
providing a semiconductor wafer having front and rear major surfaces, the wafer including a plurality of active device regions separated by scribe lanes, with top interconnection pads on the front major surface;
forming holes through the wafer within the scribe lanes;
forming an electrically insulating layer on all exposed surfaces of the wafer, including within the holes, with openings in the insulating layer for access to the top interconnection pads;
metallizing and patterning the wafer and the holes to form bottom interconnection pads and alignment pads on the rear major surface, the bottom interconnection pads electrically connected to corresponding interconnection pads by metallization extending within the holes;
employing a dicing saw having a kerf width less than the diameter of the holes to saw within at least some of the scribe lanes to separate the wafer into segments each including at least one device active region;
providing a substrate having at least two electrical connection pads positioned for mating with the alignment pads;
forming a rigid alignment structure on the substrate and projecting from the substrate for mechanical engagement with the devices; and
placing the devices on the substrate and attaching the alignment pads to the electrical connection pads, whereby the rigid alignment structure provides accurate position alignment.
2. The method of claim 1, wherein attaching comprises using solder, and further comprising employing a planarizing surface to press against the devices while the solder is allowed to solidify, whereby Z-axis alignment is also achieved.
3. The method of claim 1, wherein the rigid alignment structure formed is a set of pins or a grid-like structure.
4. The method of claim 1, wherein the alignment pads and the electrical connection pads comprise solder-wettable materials, and wherein attaching comprises soldering with the solder surface tension providing initial position alignment.
5. The method of claim 1, wherein the step of providing the substrate comprises providing a substrate in the form of a multi-chip module.
6. A method for making an array of closely-spaced imaging or display devices, comprising:
providing a semiconductor wafer having front and rear major surfaces, the wafer including a plurality of active device regions on the front major surface separated by scribe lanes, with top interconnection pads on the front major surface;
forming holes through the wafer within the scribe lanes;
forming an electrically insulating layer on all exposed surfaces of the wafer, including within the holes, with openings in the insulating layer for access to the top interconnection pads;
metallizing and patterning the wafer and the holes to form bottom interconnection pads on the rear major surface electrically connected to corresponding to interconnection pads by metallization extending within the holes;
sawing within at least some of the scribe lanes to separate the wafer into segments each including at least one device active region;
placing and attaching the segments front major surface down on an optically transparent substrate;
forming a multilayer interconnect structure overlying the rear major surfaces of the wafer segments in electrical connection with the bottom interconnection pads.
7. The method of claim 6, wherein the optically transparent substrate is rigid.
8. The method of claim 6, wherein the substrate comprises a stretched polymer film.
9. The method of claim 6, which further comprises, after the step of placing and attaching the segments, employing a molding material to fix the segments in place.
10. A method for making an array of closely-spaced devices, comprising:
Providing a semiconductor wafer having front and rear major surfaces, the wafer including a plurality of active device regions on the front major surface separated by scribe lanes, with top interconnection Dads on the front major surface;
forming holes through the wafer within the scribe lanes;
forming an electrically insulating layer on all exposed surfaces of the wafer, including within the holes, with openings in the insulating layer for access to the top interconnection pads;
metallizing and patterning the wafer and the holes to form bottom interconnection pads on the rear major surface electrically connected to corresponding to interconnection pads by metallization extending within the holes;
sawing within at least some of the scribe lanes to separate the wafer into segments each including at least one device active region;
placing and attaching the segments front major surface down on a substrate comprising a stretched polymer film;
forming a multilayer interconnect structure overlaying the rear major surfaces of the wafer segments in electrical connection with the bottom interconnection pads employing a curved tool to establish an array curvature.
11. The method of claim 6, which comprises forming a rigid alignment structure on the substrate prior to placing and attaching the segments.
12. A method for making a multi-device electronic package including a plurality of devices having major surfaces, with interconnection pads on one of the major surfaces, said method comprising:
providing a substrate and forming a rigid alignment structure on the substrate and projecting from the substrate for mechanical engagement with the devices;
placing and attaching the devices to the substrate with the interconnection pads facing up, whereby the rigid alignment structure provides accurate position alignment; and
forming a multilayer interconnect structure overlying the devices and interconnecting selected ones of the interconnection pads.
13. The method of claim 12, wherein the rigid alignment structure formed is a set of pins or a grid-like structure.
14. A method for fixing an array of electrical devices having front and rear major surfaces in precise locations on a support substrate, said method comprising the steps of:
forming a rigid alignment structure on the substrate and projecting from the substrate for mechanical engagement with the devices; and
placing and attaching the devices to the substrate, whereby the rigid alignment structure provides accurate position alignment.
15. The method of claim 14, wherein attaching comprises using solder, and further comprising employing a planarizing surface to press against the devices while the solder is allowed to solidify, whereby Z-axis alignment is also achieved.
16. The method of claim 14, wherein the rigid alignment structure formed is a set of pins or a grid-like structure.
17. The method of claim 14, which further comprises:
forming at least one solder-wettable rear alignment pad on the rear major surface of each of the devices by
providing a semiconductor wafer having front and rear major surfaces and including a plurality of device precursors,
forming alignment holes through the wafer located with reference to features on the front major surface, and
employing the alignment holes as reference points for positioning the rear alignment pads; and
for each of the devices, forming at least one solder-wettable placement pad on the substrate positioned for mating with the at least one solder-wettable rear alignment pad.
18. The method of claim 17, which comprises forming the alignment holes in dicing saw lanes between the device precursors where a dicing saw is subsequently employed to separate the device precursors into individual devices.
19. The method of claim 18, which comprises forming alignment holes having diameters greater than the dicing saw kerf width.
20. The method of claim 18, which comprises forming the alignment holes in unused areas of the device precursors.