IPC分类号：
F21L4/02 | F21V29/02 | F21V29/00
国民经济行业分类号：
C4350 | C3545 | C3871
当前申请(专利权)人：
PRINCETON OPTRONICS INC.
原始申请(专利权)人：
PRINCETON OPTRONICS INC.
当前申请(专利权)人地址：
1 ELECTRONICS DRIVE, 08619, MERCERVILLE, NEW JERSEY
发明人：
SEURIN, JEAN F. | GHOSH, CHUNI L. | WANG, QING | WATKINS, LAURENCE S.
摘要：
VCSEL arrays with planar electrical contacts readily adaptable for surface mounting are provided. Monolithic VCSEL arrays are configured in array patterns on two and three-dimensional surfaces for configuring optical illuminator modules. Illuminator modules are easily expandable by increasing the array size or by modularly arranging more arrays with or without a transparent substrate, in different shapes by tiling array modules monolithically on a common substrate, or by tiling small modules. The surface mountable illuminator modules are easily assembled on a thermally conductive surface that may be air or liquid cooled for efficient heat dissipation. Array modules may be integrated with other electronic circuits such as current drivers, sensors, controllers, processors, etc. on a common platform, for example, a single or multiple layer printed circuit boards (PCB) to assemble illumination systems for different applications including a gesture recognition apparatus and a battery operated portable illuminator devices.
技术问题语段：
The technical problem addressed in this patent text is to provide a surface mountable optical illuminator that is robust and efficient, and can be used as a surface mount component or as a stand-alone module. The solution involves bonding VCSEL array(s) to a transparent carrier substrate that seals the emission surface and also includes a diffuser to adjust the illumination pattern.
技术功效语段：
The patent text describes a new way to create an optical module with an array chip that can be easily mounted on a circuit board and can be expanded for increased output. The module can be made smaller and more portable for airborne operation or for use in other three-dimensional shapes. The invention also eliminates the need for wire bonding and via holes through the substrate, making it more efficient and easier to operate. A portable illuminator can also be created using the invention.
权利要求：
1. A portable illuminator comprising:
a cylindrical enclosure, said cylindrical enclosure further including;
an optical illuminator located on one end of the cylindrical enclosure, wherein the optical illuminator includes a plurality of VCSEL arrays mounted on an outer surface of a hemispherical member, said VCSEL arrays are electrically connected to emit light collectively;
a transparent protective surface disposed on the outer surface of the hemispherical member for protecting the plurality of VCSEL arrays, wherein said protective surface further includes a diffuser surface for directing the emission beam from the plurality of VCSEL arrays into a uniform illumination pattern;
a pump, said pump connected with a cooling tube to a liquid coolant source for providing a liquid coolant at high pressure, to an inner surface of the hemispherical member that is in physical and thermal contact with the plurality of VCSEL arrays located on the outer surface of the hemispherical member;
a printed circuit board including one or more electronic circuits electrically connected to the plurality of VCSEL arrays;
a battery chamber located at an opposite end from the hemispherical member for providing portable power source to operate the portable illuminator.
2. The portable illuminator as in claim 1, wherein each one of the plurality of VCSEL arrays further include:
at least one array comprising a plurality of VCSELs, wherein all the VCSELs are configured to emit light in a direction perpendicular to an emission surface of the array, said emission surface further including a plurality of emission windows, each emission window substantially aligned with a respective VCSEL of said array, said array further including a first electrical contact located on the emission surface and a second electrical contact located on an opposing non-emission surface of the array, respectively;
a trench located on the non-emission surface of the array, said trench for electrically isolating the array from an electrical contact region located on the non-emission surface;
an electrically conducting path for providing electrical connectivity between the first electrical contact located on the emission surface and the contact region on the non-emission surface co-planar with the second electric contact, so as to facilitate surface mounting of the illuminator module; and
a transparent carrier substrate disposed on the emission surface, said carrier substrate further including an electrical contact layer, wherein the electrical contact layer further includes a second plurality of windows substantially matching with the plurality of emission windows on the emission surface of the at least one array, such that the emission is directed out of the carrier substrate from a surface distal to the array module.
3. The portable illuminator as in claim 1, wherein the diffuser comprises thin sheets of optical diffuser.
4. The portable illuminator as in claim 1, wherein the one or more electronic circuit includes a current driver, an image sensor, a camera, a controller, and a processor or a combination thereof.
5. An optical illuminator comprising:
a three dimensional illuminator head having a thermally conductive surface;
a plurality of Vertical Cavity Surface Emitting Lasers (VCSEL) arrays mounted in thermal contact with the illuminator head, such that said plurality of VCSEL arrays cover the thermally conductive surface; and
one or more electronic circuits electrically connected to the plurality of VCSEL arrays to emit light collectively in a direction that is away from the thermally conductive surface.
6. The optical illuminator as in claim 5, wherein geometric shape of the illuminator head is one selected from the group consisting of a sphere, a hemisphere, a parallelepiped, a cone, and a pyramid.
7. The optical illuminator as in claim 5, wherein the plurality of VCSEL arrays covers the thermally conductive surface completely so as to provide illumination along the surface of the illumination head.
8. The optical illuminator as in claim 5, wherein the plurality of VCSEL arrays covers the thermally conductive surface in a pre-determined geometrical pattern so as to provide a desired illumination pattern.
9. The optical illuminator as in claim 8, wherein different sections of the geometrical pattern are illuminated in a pre-determined timing sequence.
10. The optical illuminator as in claim 5 further including a heat dissipation device in physical contact with the illuminator head, wherein the heat dissipation device is cooled using a circulating fluid.
11. The optical illuminator as in claim 5, wherein the illuminator head is a hollow member comprising a geometric shape that is one selected from the group consisting of a sphere, a hemisphere, a parallelepiped, a cone, and a pyramid, and wherein the thermally conductive surface is the outer surface of the illuminator head.
12. The optical illuminator as in claim 11, further including a heat dissipation device, such that the heat dissipation device located in physical contact with the hollow region cools the inner surface of the illuminator head.
13. The optical illuminator as in claim 12, wherein the heat dissipation device includes a cooling tube in physical contact with the inner surface of the illuminator head in one or more places, said cooling tube is connected to a circulating cooling fluid source through a pump for pumping a cooling fluid at high pressure in the cooling tubes to cool the thermally conductive surface.
14. The optical illuminator as in claim 5, wherein, each one of the plurality of VCSEL arrays is monolithic, said monolithic array further including:
a plurality of VCSELs emitting light collectively in a direction perpendicular to an emission surface of the array that comprises a plurality of emission windows in a first contiguous metallized layer located on the emission surface of the array, each emission window being substantially aligned with a respective VCSEL of said array, wherein said first metallized layer in electrical contact with the VCSELs provides a common first electrical contact, and a second metallized layer in electrical contact with the VCSELs and located on an opposing non-emission surface provides a common second electrical contact, respectively, to the at least one array;
a trench located on the non-emission surface of the array, said trench electrically isolating the second electrical contact of the array from an electrical contact region located on the non-emission surface; and
an electrically conducting path connecting the first electrical contact located on the emission surface to the electrical contact region located on the non-emission surface, such that the first electrical contact and the second electric contact are coplanar and accessible on the non-emission surface for surface mounting.
15. The optical illuminator as in claim 5, wherein the plurality of VCSEL arrays is supported on one or more thermally conducting submount to facilitate the thermal contact between said plurality of VCSEL arrays and the illuminator head.
16. The optical illuminator as in claim 5 further including an encapsulation disposed over the plurality of VCSEL arrays, said encapsulation having optional optical device that is one selected from the group consisting of a protective transparent window, a lens, a lens array, a diffuser, and a combination thereof.
17. The optical illuminator as in claim 5, wherein each one of the plurality of VCSEL arrays further includes:
a plurality of monolithically constructed VCSELs that emit light in a direction perpendicular to an emission surface of the array chip, said emission surface further including a plurality of emission windows, each emission window substantially aligned with a respective VCSEL of said array, said array further including a first electrical contact located on the emission surface and a second electrical contact located on an opposing non-emission surface of the array, respectively;
a trench located on the non-emission surface of the array, said trench for electrically isolating the array from an electrical contact region located on the non-emission surface;
an electrically conducting path for providing electrical connectivity between the first electrical contact located on the emission surface and the contact region on the non-emission surface co-planar with the second electric contact, so as to facilitate surface mounting of the illuminator module; and
a transparent carrier substrate disposed on the emission surface, said carrier substrate further including an electrical contact layer, wherein the electrical contact layer further includes a second plurality of windows substantially matching with the plurality of emission windows on the emission surface of the at least one array, such that the emission is directed out of the carrier substrate from a surface distal to the array module.
18. The optical illuminator as in claim 5, wherein the one or more electronic circuits include a current driver, a controller and a processor such that the optical illuminator is configured to function as a high intensity three dimensional continuous wave (CW), quasi-continuous wave (QCW) or a pulsed lighting source.
19. The optical illuminator as in claim 5, wherein the one or more electronic circuit includes a current driver, a controller, and a processor or a combination thereof.
20. The optical illuminator as in claim 19 further including an image sensor and a camera, such that the optical illuminator is configured to function as a three dimensional motion sensor or gesture recognition apparatus.
技术领域：
[0003]The present invention relates to optical illumination systems and in particular to an optical illuminator using arrays of Vertical Cavity Surface Emitting Lasers (VCSEL) configured with a three dimensional illumination surface.
背景技术：
[0005]Optical illumination is widely used in a large number of applications whether applied to reflect incident optical radiation, such as optical imaging, or medical imaging, etc. or applied to absorb incident radiation, such as optical pumping of a gain medium in a solid state laser. New and more efficient optical sources are emerging that may be suitable for applications that require small foot print, higher uniformity, high speed or quasi-continuous wave (QCW) illumination, just to name a few. One such class of new optical sources is configured using Vertical Cavity Surface Emitting Lasers (VCSEL) and arrays of VCSELs.
[0006]One advantage of VCSELs is that the divergence angle of emitted light is very small. Consequently, emission from VCSELs is highly directional even at large distances from the origin. VCSEL emission in visible and infrared wavelengths may be obtained in a very narrow wavelength band allowing optically efficient filtering of background noise. VCSELs are also amenable to generating short pulses, thereby making these sources suitable for LIDAR type applications and for time domain distance discrimination applications such as seeing through fog and motion and gesture detection, etc.
[0007]Current technology for packaging VCSELs is quite complex. In most instances, packages typically have electrical leads that are designed for through hole mounting on electronic circuit boards and are described in many prior art patent and non-patent literature publications. In a co-authored and co-owned pending U.S. patent application Ser. No. 13/337,098 filed on Dec. 24, 2011, by Seurin et al, a surface mount packaging is disclosed, the content of which is hereby incorporated by reference in its entirety. More specifically, a single VCSEL and/or arrays of VCSELs are mounted on a thermal submount and then installed in surface mountable housing. The thermal submount may be bonded to a thermal substrate, or in a housing including external cooling devices, by solder or epoxy. The VCSEL or arrays of VCSELs are electrically connected to the submount and to the package conductor pads, using wire or ribbon bonding.
[0008]Similar approach of a surface submount is also disclosed in other patents and patent application publications. For example, in the U.S. Pat. No. 7,777,173 issued to Price et al. on Aug. 10, 2010, in the United States Patent Application Publication No. 2003/0185499 A1 by Butler et al. published on Oct. 2, 2003, and in United States Patent Application Publication No. 2006/0088254 A1 by Mohammed published on Apr. 27, 2006. In some of the submounts described in the cited prior art, additional optical elements are included for controlling beam shape.
[0009]The beam divergence of VCSEL is quite small and typically has a Gaussian or pseudo-Gaussian distribution. Depending on the application it is often required to adjust the illumination pattern by either increasing the divergence or by changing the distribution from the Gaussian distribution to approximately a top-hat distribution. In other types of mounting configuration well known in the art, a diffuser to adjust a beam distribution pattern is used. For example, in the U.S. Pat. No. 5,946,121 issued to Jiang et al, on Aug. 31, 1999, use of a diffuser attached to the package lid to increase the divergence of a single emitter in a data link application is described. In the United States Patent Application Publication No. 2008/0310852 by Tan et al, published on Dec. 18, 2008, a diffuser is provided to compensate for misalignment in an optical communications transmitter comprising a single VCSEL emitter.
[0010]Diffusers alone, or in combination with other optical components, are used with VCSEL and VCSEL arrays as described in many other publications. A diffuser to reduce the coherence in an array of different colored emitter for electronic imaging is disclosed in a U.S. Pat. No. 6,950,454 issued to Kruschwitz on Sep. 27, 2005. However, no detailed description is provided about how the diffuser is attached in the system especially since the diffuser has to be vibrated to eliminate speckle effects. In the United States Patent Application Publication No. 2008/0079904 by Bartlett, published on Apr. 3, 2008, layouts of VCSEL arrays in combination with diffuser in complex alignment with other optical components, is described to generate a uniform illumination beam.
[0011]In a different application described in the U.S. Pat. No. 7,150,552 issued to Weidel on Dec. 19, 2006, a diffuser is placed close to the collection lens to obtain a uniform beam from a VCSEL array. In all of the above examples, the diffuser is an additional optical component bonded to a separate fixture, located a distance away from the laser emitter and requires accurate alignment and positioning.
[0012]In other arrangements, a diffuser may be placed in close proximity to the VCSEL or VCSEL array. For example, in the U.S. Pat. No. 7,949,022 issued to Miesak et al on May 24, 2011, a diffuser plate in placed proximal to a VCSEL array for optically pumping a solid state laser. The diffuser is close to the VCSEL array but requires a separate mounting to hold it in place between the VCSEL array and the solid-state laser crystal. In an alternative arrangement, individual diffusers separately bonded to each VCSEL in an array is described in the United States Patent Application Publication No. 2003/0026310 by Valliath, published on Feb. 6, 2003. This approach requires aligning each diffuser individually over the emitter and then bonding it in place. For larger arrays having many emitting devices the assembly procedure becomes very expensive.
[0013]In this invention a robust and efficient surface mountable optical illuminator is provided that can be used as a surface mount component or as a stand-alone module. The illuminator comprises VCSEL array(s) bonded to a transparent carrier substrate (carrier substrate hereinafter) which seals the emission surface and also provides a robust support. One advantage of the surface mountable packaging option is to avoid wire or ribbon bonding of VCSEL arrays that may become a cause of device failure over long run and that increase module costs. The emitting or non-emitting surface of the VCSEL or VCSEL arrays may be integrated with electronic circuit(s) to electrically connect illuminator module to a drive and/or control circuit(s) on a circuit board using standard surface mounting methods.
[0014]The carrier substrate is designed to optionally include optical components such as microlenses, diffusers, etc. The VCSEL array with the carrier substrate may be adapted for surface mounting on a circuit board or a submount as the application demands. In one adaptation of the invention, surface mountable VCSEL arrays may be disposed on a surface of a three dimensional member adapted for surface cooling using a circulating fluid for example, a gas including air, or a liquid. In another adaptation, a three dimensional configuration is used as a portable illuminating device. The optical illuminator as disclosed in this invention does not require intricate alignment of optical components with individual VCSELs in the array, thereby is readily adaptable for high throughput manufacturing.
发明内容：
[0015]In one embodiment of the invention a VCSEL array illuminator module is provided that is designed for surface mounting either alone, or integrated with electronic circuit(s) on a circuit board, for example a printed circuit board (PCB) or on a heat management equipment. VCSEL array module comprises a VCSEL array chip and a carrier substrate configured to function as a protective window on the emitting surface. In a variant embodiment, the carrier substrate window includes additional optical elements for providing beam shaping functions.
[0016]One aspect of the invention is to provide an electrical contact from the emitter side to the non-emitter side of the array chip, such that both the terminals of the array chip are accessible on the same side of the module, thereby providing surface mounting capability. Advantageously, an optical module constructed according to this invention eliminates the need for wire or ribbon bonding, and/or via holes through the substrate.
[0017]According to one aspect of the invention, surface mountable array modules are provided by connecting the emitter side terminal of the array chip to a connector pad on the non-emitter side of the array chip by an additional metal connector or a metal track, deposited in an open window or a trench in the VCSEL array chip. The additional metal track connects the emitter side terminal to the connector pad on the non-emitter side using a connector bridge on the metal pad on the carrier substrate. In another embodiment, an electrical contact from the emitter side to the non-emitter side of the array chip is provided by using a metal bump on the non-emitter side of the array chip. Advantageously, the surface mounting connector pads are configured in a co-planar form without wire or ribbon bonding or via holes through the substrate by a wafer level process prior to dicing and separating of the individual arrays.
[0018]One aspect of the invention provides metal bonding pads on the carrier substrate that are aligned with corresponding metal bonding pads on the VCSEL array chip, such that the carrier substrate and the VCSEL array chip are reliably bonded for example, using metal-to-metal planar contacts. The bonding pads on the carrier substrate may be designed to bond more than one array chip that are electrically connected in parallel or in series. To expand the size of the array module or to increase the output optical power, the array chips are arranged in tiles. In a variant embodiment, the array chips are tiled to configure array module of specific shapes. As one aspect of the invention the tiling processes may be performed at chip or wafer level.
[0019]In another embodiment, multiple array modules are assembled to modularly expand the illumination area and/or power output. Multiple array modules bonded to a respective carrier substrate may be assembled individually on a common submount including a thermally conducting submount. In an alternative embodiment, a plurality of array chips are bonded to a single carrier substrate and electrically connected using additional metal tracks specifically designed to provide parallel or series connectivity for expanding the array module.
[0020]In another variant embodiment the array chips are designed to have planar contacts that are adaptable for surface mounting. An array chip may be designed to include one or more VCSEL arrays that may be electrically connected in parallel or series to configure larger array chips. A larger array chip is then bonded in a single bonding operation, to a carrier substrate having corresponding metal bonding pads so as to configure an array module.
[0021]In a different embodiment, an optical illuminator comprising one or more VCSEL array modules is provided. The optical illuminator may be configured as a surface mountable module or as a stand-alone illuminator by integrating electronic circuit(s) with the illuminator module on a common printed circuit board (PCB). The electronic circuit(s) provides operation and control functions, such as drive current and/or logic control, signal detection, etc. to the illuminator. The array module and the electronic circuit(s) are adapted for surface mounting. Electrical connection between the array module and one or more electronic circuit(s) may be provided on a common level of the PCB, or on multiple levels of a multi-level PCB. Advantageously, the illuminator modules provided in this invention may be expanded in a modular fashion to increase the surface area and/or optical power output.
[0022]In one embodiment of the invention an illuminator module is surface mounted with or without one or more electronic circuit(s) on a common thermally conductive platform to provide a means for heat management. Thermally conductive platform may be designed to include elements that would reduce parasitic electrical components and in particular, the inductance of the driving circuit for high speed or Quasi Continuous Wave (QCW) operation of the illuminator module. Thermally conductive platform may be further attached to a heat dissipation surface that may be air cooled or liquid cooled.
[0023]In a different embodiment, an illuminator module is provided with encapsulation. The encapsulation may be applied to an array module or a group of array modules assembled on a common platform or to an array module or a group of array modules in combination with one or more electronic circuit(s) assembled on a PCB. Encapsulation may be applied to perform additional optical functions such as a focusing lens or as a window. In a variant embodiment, the encapsulation may be provided using an enclosure having a window. The window may include additional optical components for providing beam shaping functions. In yet another embodiment, the substrate of the VCSEL array module may be shaped to provide microlenses on the emitter surface.
[0024]One aspect of the invention is to provide an illuminator module configured in a system with one or more electronic components or circuits for specific applications. In one embodiment a motion or gesture recognition apparatus is provided by integrating an illuminator module with a sensor device and operating and control electronics. Advantageously, the small form factor of the apparatus is conducive for portability and inclusion in a variety of consumer devices requiring a motion or gesture recognition capability.
[0025]In another embodiment a portable illuminator is provided. The VCSEL array chips are provided on a water cooled surface of a three dimensional structure, for example a hemispherical object, to provide a wide angle illumination of a scene. Advantageously, the small form factor portability facilitates airborne operation of the portable illuminator in certain scene illumination applications. Alternatively, illuminator may be adapted for other three dimensional shapes depending upon the application that may include portable or stationary illumination, motion sensor, and gesture recognition.
具体实施方式：
[0050]Various aspects of this invention representing a broad framework of the principles will be described using exemplary embodiments and represented in different drawing figures. For clarity and ease of description, each embodiment includes only a few aspects. However, different aspects presented in each embodiment may be practiced separately or in various combinations. Many different combinations and sub-combinations of the representative embodiments within the broad framework presented in this written specification, may be apparent to those skilled in the art but not explicitly shown or described, should not be construed as precluded.
VCSEL Array Chip
[0051]Referring now to FIG. 1, there it shows several individual VCSEL devices and a VCSEL array constructed of VCSEL devices that are used in configuring optical illuminators to be described in detail. For clarity and ease of description, only basic two terminal VCSEL devices emitting in a direction perpendicular to plane of the substrate, are shown here. It should be noted that other advanced VCSEL devices emitting perpendicular to the substrate plane are equally applicable for constructing VCSEL array illuminator and are not precluded.
[0052]In FIGS. 1a, 1b and 1c elements that are labeled using same reference numerals are either identical or provide similar functions. A description in reference with any reference numeral is equally pertinent for a similar element in all the embodiments. More specifically, a simple two terminal VCSEL device shown in FIGS. 1a, 1b and 1c is constructed on a substrate 101. Each device comprises a light emitting region including an optical gain region 104 comprising one or more quantum well p-n junctions. More advanced VCSEL devices may also include other types of junctions, such as a tunnel junction, a homojunction, a heterojunction, etc., that are well known in the art. The light emitting region in these examples is constructed by epitaxial growth. It may be understood that the light emitting region may often be referred synonymously as epitaxial region in the following description.
[0053]The light emitting region comprises the optical gain region disposed in a vertical laser cavity formed by reflectors 103 and 106, respectively. The reflectors may include but are not limited to, semiconductor distributed Bragg reflector (DBR), dielectric mirrors, optical gratings or a combination thereof. For example, in FIG. 1c, commonly known as an “intra-cavity contacted” structure, reflector 106 is a hybrid reflector comprising two sections, a semiconductor distributed Bragg reflector (DBR) 106a and a dielectric coating reflector 106b. Electrical contact layers 102 and 107 to the VCSEL structure is provided respectively, on the substrate side and on the reflector 106 (in FIGS. 1a and 1b) and on the semiconductor reflector 106a (FIG. 1c). The electrical contacts function as the terminals for the VCSEL device.
[0054]A current confinement aperture 105 controls the flow of drive current to the light emitting region and also determines the emission area and the shape of emission beam, as has been described in the co-authored and co-owned pending U.S. patent application Ser. No. 13/337,098 by Seurin et al., filed on Dec. 24, 2011. That description is incorporated by reference in its entirety. The current confining aperture can be formed via a selective oxidation process, an implantation process, a buried tunnel junction process, a re-growth process, or other methods that are well known in the art. In these examples the devices are shown with their respective substrates. It is a common practice to reduce the thickness of the substrate or completely remove the substrate to reduce absorption of the emitted light in the substrate (in devices where the substrate would absorb the emitted light completely), and for facilitating efficient heat dissipation.
[0055]Light emission 109 from the device may be output from a window 108 that may be placed on the reflector side, or from the substrate side. More specifically, light emission is from the window 108 located on the reflector 106 and 106b, respectively, in the ‘top’ emission devices shown in FIGS. 1a and 1c whereas light emission is from the window 108 located on the substrate side in the bottom emitting device shown in FIG. 1b, respectively. It should be noted that the bottom emitting device shown in FIG. 1b is mounted with the substrate side up such that the light emission in the devices is in an upward direction (arrow 109). The convention for upward emission followed here is exemplary and not to be construed as limiting.
[0056]It can be appreciated by those skilled in the art that instead of a single VCSEL device, an array of multiple VCSEL devices may be constructed monolithically on a single common substrate as shown in FIG. 1d. More specifically, a device 110 shown therein comprises a two-dimensional array 111 of a plurality of VCSEL devices (each dot represents a VCSEL device) similar to those shown in FIGS. 1a, 1b and 1c, constructed on a common substrate. In this particular example, the VCSEL devices are arranged to form a circular array chip. It can be appreciated that array chips may be configured in any regular geometric pattern or in a random shape. All the VCSELs in the array are electrically connected to the substrate which functions as a first common terminal 112 of the array. In order for the VCSELs to emit collectively, the second electrical contact of each VCSEL in the array is connected using a common metallization 117 disposed contiguously on the array surface which functions as a second common terminal of the array. The common metallization has a plurality of windows substantially aligned with the current confining apertures of the respective VCSEL devices in the array.
[0057]In this example, all the VCSEL devices in the array emit collectively in an upward direction shown by the arrow 119. For the ease of description, the VCSEL array as shown in FIG. 1d will be referred as VCSEL array chip (or array chip hereinafter). It may be recalled that the VCSELs in the array chip may be top or bottom emission types; accordingly the array chip needs to be mounted substrate down or up, respectively. Irrespective of the top or bottom emission devices in the array chip, for the clarity and ease of discussion and not as a limitation, following convention is adopted; the emission surface of the array chip will be referred as the emission end or top end of the array chip whereas, the opposite end will be referred as the non-emission end or bottom end of the array chip. Similar convention will be followed for a top and bottom contact of the array chip. In the example shown in FIG. 1d, the first common terminal or the bottom contact 112 is located on the non-emission end, whereas the second common terminal or the top contact 117 is located on the emission end.
[0058]The array chip may be further mounted on a heat dissipating device 120 with its non-emission end in contact with the heat sink. The heat dissipating device may include but is not limited to, a thermal submount similar to ones described in the co-authored and co-owned pending U.S. patent application Ser. No. 13/337,098 by Seurin et al., filed on Dec. 24, 2011. That description is being incorporated by reference in its entirety. Heat dissipating device may be cooled by a fluid for example, a gas including air, or liquid, depending upon the size and the output optical power of the array chip.
[0059]It is noted that the two terminals of the exemplary array chip shown in FIG. 1d are located on two opposite ends (emission and non-emission ends) of the array chip. This aspect is more clearly depicted in cross section schematic views shown in FIG. 2. In the embodiments shown in FIGS. 2a-2d, identical elements are labeled with same reference numeral to keep the description clear and short. Each element will be described once and that description is equally pertinent to all the embodiments shown in FIG. 2, unless mentioned otherwise. The top and bottom ends (and electrical contacts) of the array chip will be referred with respect to the emission surface following the convention developed in reference with FIG. 1d.
[0060]Referring now to FIGS. 2a-2d, an array chip is constructed on a common substrate 201 in each instance. For clarity of representation, the VCSEL array active layer comprising the light emitting region, the current confining region and the reflectors (respectively, 104, 105, 103, 106 in FIGS. 1a and 1b and 1c) is collectively represented as 220. In the top emission configuration of the array chip shown in FIG. 2a, the bottom contact 202 on the non-emission side forms a common first terminal of the array chip. The bottom contact is a continuous metallization layer which is electrically connected to the conducting substrate (201) in this example.
[0061]The top contact disposed on the active layer on the emission side forms a common second terminal of the array chip. The top contact comprises a continuous metallization layer having emission windows 208 (only one labeled for clarity) created by selective etching (or selective deposition). The metallization between the windows form the top metal contact pads 207 (only one labeled) for making electrical connections. Each window (208) is aligned with a corresponding current confinement aperture of a VCSEL located directly below.
[0062]In the bottom emission configuration shown in FIG. 2b, the array chip is placed upside down such that the non-emission side contact 202 electrically connected to the active layer forms a common first terminal. The top metallization layer on the emission side is disposed on the substrate 201 and has a plurality of windows 208 (only one labeled). The remaining metallization layer contiguous between the windows form electrical contact pads 207 (only one labeled) for making electrical connections. Each window (208) is substantially aligned with a corresponding current confinement aperture in the active layer located directly underneath. The top metallization layer forms a common second terminal for the array chip. The array chip in bottom emission mode is upside down, such that the emission is from the substrate end in an upward direction (209). However, the example shown here in this configuration is not to be construed as limiting.
[0063]In the array chips shown in FIGS. 2a and 2b, the first and second terminals are located on the opposite sides of the emission surface. In order to facilitate surface mounting, it is desirable to have both the electrical terminals as planar contacts located on the same side. FIGS. 2c and 2d show two embodiments where the first and second terminals are located on the same side. More specifically, the array chip is mounted in the bottom emission mode in the embodiments shown in FIGS. 2c and 2d, (similar to the embodiment shown in FIG. 2b); however, it should not be construed as a limitation.
[0064]In the embodiment shown in FIG. 2c, a window 221 or a trench is created by selectively removing a part of the bottom contact 202 and the active layer 220 underneath. It is noted that a common general meaning of a ‘trench’ namely, a narrow and long opening on a surface, where the length of the opening is substantially larger than the width, applies in this context as well. An additional metallization layer 222 is selectively deposited on the non-emission side of the substrate 201. The metallization layer 222 is supported on the part of the active layer that is physically and electrically separated from the rest of the active layer of the array chip by the window 221. The conductive substrate having contact on both sides in this configuration electrically connects the metallization layer 222 to the top contact 207 through current flow in the substrate. Thus, the two terminals of the array chip (222 and 202) having substantially the same height, are co-planar on the same side of the array chip, thereby facilitating surface mounting of the array chip.
[0065]The embodiment shown in FIG. 2d is slightly different; a portion of the bottom contact 202 and the active layer underneath is selectively removed. An electro-plated gold bump 223 substantially equal in height to the active layer 220 and the contact layer 202, is then deposited on the non-emission side of the substrate 201 leaving a gap 221 between the array chip active layer and the gold bump 223. Thus the conductive substrate having contact on both sides in this configuration electrically connects the gold bump 223 to the top contact 207 through current flow in the substrate. Therefore the two terminals of the array chip are co-planar on the same side. In the configurations described in FIGS. 2c and 2d, the gap 221 may optionally be filled with an insulating or a polymeric material using a process step known as ‘planarizing’ in the art.
[0066]Although the concept of surface mountable VCSEL array chip is demonstrated using a bottom emitting array chip, the same concept is equally applicable for top emitting array chip. As mentioned earlier, the substrate may be thinned down or entirely removed to reduce absorption of the emitted light in the substrate (in devices where the substrate would absorb the emitted light completely), and for facilitating efficient heat dissipation.
[0067]In one variant embodiment shown in FIG. 3, additional optical functionality is provided by integrally constructing optical components to a surface mountable VCSEL array chip substantially similar to the one described in reference with FIG. 2c. More specifically, in FIG. 3, a VCSEL array chip comprises an active layer 320 disposed on a substrate 301. Part of the active layer 320 is selectively removed to create a trench 321 to facilitate connecting the top electrical contact layer 307 to an additional metallization layer 322 on the non-emission side of the substrate.
[0068]A microlens array comprising of a plurality of microlenses 326 is constructed on the emission end of the array chip such that each microlens in the array matches a corresponding window 308 (only one microlens and window is labeled for clarity) on the emission end. The microlens array may be constructed by selectively etching the substrate or by a post processing step. Different options available for post processing steps are well known in the art and will not be described. The height and curvature of the microlenses may be pre-determined to provide a desired functionality for example, beam shaping by focusing or collimating the emission from each VCSEL in the array chip. It is also possible to construct different microlenses having different optical properties in different sections of the array chip.
[0069]One advantage of the surface mountable array chip constructed according to this invention is that the manufacturing process is simplified by reducing or eliminating complex alignment steps currently used for creating via holes through the substrate. The invention also provides a means to eliminate wire or ribbon bonding of the top (emission side) contact to a connector pad on the bottom (non-emission) side of the array chip. It should be noted that the applicants in a co-authored and co-owned prior U.S. patent application Ser. No. 13/337,098 by Seurin et al., filed on Dec. 24, 2011, described a surface mountable VCSEL array module where the contact from the top emission side of the VCSEL array is connected to a contact pad on a thermal submount on the non-emission side using a wire or ribbon bonding. Those skilled in the art will be able to recognize that the wire or ribbon bonded contacts are often the cause of device failure and also increase costs. The surface mountable array module described in this invention substantially reduces that risk by using only co-planar contacts.
VCSEL Array Module
[0070]In one embodiment of the invention, surface mountable array chips described in the previous section are used to construct VCSEL array optical module (array module hereinafter). FIG. 4 shows an optical module constructed using a top emitting array chip similar to the one shown in FIG. 2a. The elements that are identical in different embodiments shown in FIGS. 4a, 4b and 4c are labeled with the same reference numerals. Referring now to array modules shown in FIGS. 4a, 4b, and 4c, section 400 collectively represents an array chip substantially similar to the one shown in FIG. 2a.
[0071]More specifically, the array chip shown in FIG. 4a comprises an active layer 420 disposed on a substrate 401. The array chip configured in the top emission mode includes a plurality of emission windows 408 (only one labeled) opened on a continuous metallization layer leaving the surrounding contiguous areas as metal pads 407 (only one pad labeled) for making electrical contacts on the emission side. The contiguous metal pads form a first terminal of the array module. A second section 410 of the module comprises a transparent carrier substrate 411 (carrier substrate hereinafter). The bottom and top surfaces of the carrier substrate are coated with antireflection layers 412 and 413, respectively. A continuous metallization layer 414 is disposed over one of the antireflection layers 412 (in this example). The metallization layer may be selectively deposited using a mask, or selectively removed, to open windows on the metallization layer, while the remaining contiguous metallization layer around the windows form metal pads for making electrical connections and bonding. The windows on the array chip and the carrier substrate may be created using the same mask set, such that the windows and the surrounding pads in the two sections align.
[0072]The carrier substrate 410 is flipped and bonded to the array chip at the metal pads by soldering, for example. However, other methods for bonding such as capillary bonding may also be used. The windows and the surrounding pads in the two sections align upon bonding the two sections. A portion of the active layer and the substrate is selectively removed to create a window or a trench 421 for connecting the top electrical contact of the array chip to a contact pad on the non-emission side. In an alternative embodiment shown in FIG. 4b, after bonding the two sections, the substrate 401 is thinned, or removed entirely (in this specific example) for more efficient heat dissipation from the VCSEL array.
[0073]A continuous metallization layer 402 is deposited on the bottom non-emission surface, such that part of the window 421 is without any metallization. An additional metallization layer is deposited to create a contact pad 422 for providing an electrical contact from top metal pads 407 to the non-emission side (proximal to the substrate in FIG. 4a) of the array chip, thereby forming a first and a second terminal of the array module via the carrier substrate bridge 414 in the metallization layer. In a different embodiment shown in FIG. 4c, a portion of the active layer 420 is selectively removed to electrochemically plate a gold bump 423 on the non-emission side leaving a gap 421 between the active layer and the gold bump, substantially similar to the one described in reference with FIG. 2d. The thickness of the gold bump is substantially equal to the thickness of the active layer. In the configurations shown in FIGS. 4a, 4b and 4c the first and second electrical contacts for the array are in a planar form and located on the non-emission surface. Light from the array module 409 is emitted through the carrier substrate 410 which also seals and protects the VCSEL devices located on the array chip.
[0074]FIGS. 5 and 6 show exemplary array modules constructed from array chips shown in FIGS. 2c and 2d, respectively. Reference numerals in FIGS. 5 and 6 follow the same convention as the reference numerals in FIG. 4. Referring now simultaneously to FIGS. 2, 4, 5 and 6, the array module shown in FIG. 5a has an array chip section 500 bonded to a carrier substrate section 510 that are substantially similar to the ones described earlier in reference with FIGS. 4a and 4b. The reference numerals 511, 512, 513 and 514 represent elements that are substantially similar to the elements 411, 412, 413 and 414, respectively, described earlier in reference with FIG. 4. That description will not be repeated for brevity.
[0075]The array chip in the embodiment shown in FIGS. 5a and 5b is configured in bottom emission mode and is substantially similar to the one described in reference with FIG. 2c. The active layer 520 is selectively removed to create a trench 521 in order to deposit an additional metallization layer 522 to make an electrical connection from the top contact layer 507 on the emission surface to the non-emission side surface of the device, such that the two planar terminals (522 and 502) of the array chip are located on the non-emission side of the substrate in planar form.
[0076]The embodiment shown in FIG. 5b is substantially similar to the one described in reference with FIG. 5a except for the structure of the trench 521. In this example, the trench is extended all way to the carrier substrate by selectively removing the active layer and the substrate. The additional metallization layer 522 connects the top metallization layer 507 of the array chip using the bridge, created by the metallization layer 514. The metallization layers 522 and 502 form the two planar contacts for the array terminals located on the same side of the substrate. In the embodiments shown in FIG. 5, the light from the array module is emitted in a vertical direction (relative to the page) shown with the arrow 509.
[0077]Referring now simultaneously to FIGS. 6a and 2d, the embodiment shown in FIG. 6a comprises an array chip section 600 bonded to a carrier substrate section 610. The carrier substrate section 610 is substantially similar to the ones described in reference with FIGS. 4 and 5 and that description will not be repeated. The elements shown by the reference numerals 611, 612, 613 and 614 are described earlier in reference with similar elements 411, 412, 413 and 414 shown in FIG. 4. The array chip is configured in the bottom emission mode substantially similar to the one shown in FIG. 2d.
[0078]More specifically, a portion of the active layer 620 is selectively removed from the substrate 601. On the exposed section of the substrate, an electrical contact is made by selectively electroplating a metal layer 623 leaving a gap 621 between the active layer and the electroplated region. The electroplated contact layer is located on the same side as the contact layer 602 and the thickness of the plated region is substantially equal to the thickness of the active layer. The plated region is electrically connected to the top contact layer 607 via the substrate. The electroplated metal layer 623 and the non-emission side contact layer 602 form the two terminals of the array module. Since in this case the substrate 601 can be conducting and carry the electrical current, the metal layers 614 and 607 may not be necessary, and the substrate 601 may be bonded directly to carrier substrate 610, using well known techniques such as capillary bonding.
[0079]The embodiment shown in FIG. 6b is substantially similar to the embodiment shown in FIG. 6a and comprises two sections 600 and 610, representing an array chip and a carrier substrate section, respectively. The carrier substrate section 610 includes elements (611-614) that are substantially similar to the elements (611-614) described in reference with FIG. 6a. In addition, the carrier substrate includes an electroplated region 623 located on a part of the metallization layer 614.
[0080]The carrier substrate section is bonded to the array chip 610 by aligning the metal pads 607 with a corresponding metal pad 614 and pressing them together and in some cases fusing them with heat, such that the windows 608 align with the windows in the substrate. Soldering techniques can be also used to attach 607 to 614. The metal pads 607 are electrically connected with the electroplated layer via the metal bridge of the metallization layer 614 on the carrier substrate. The metallization layer 602 and 623 form the two terminals of the array module located on the non-emission side of the substrate. The light emission shown by the arrow 609 is in the vertical direction (with reference to the page) from the top surface of the array chip substrate.
[0081]There are several advantages of constructing the surface mountable array modules according to this invention. One advantage is that the top contact on the emission surface is connected to the non-emission side of the module using planar contacts (without wire or ribbon bonding), which reduces the risk of failure considerably. The invention also eliminates the need for the complex alignment steps used in conventional surface mountable devices for the alignment of via holes through the substrate. Furthermore, the array chip is bonded to the carrier substrate using a metal-metal solder or fusion bonding between the pads which is more robust as compared to epoxy bonding often used for this purpose in prior art devices. Other bonding methods such as capillary bonding may also be used. In addition, different sections may be pre-fabricated separately and assembled in a modular fashion in a relatively shorter time, thereby improving throughput in a manufacturing environment and reducing cost. It should be noted that the principles of the invention is described using planar contacts, the same principles may be applied to other surface mountable VCSEL arrays using wire or ribbon bonding. However, those skilled in the art would be able to appreciate the merits of the planar contact options over other connector options described in the co-authored and co-owned pending U.S. patent application Ser. No. 13/337,098 by Seurin et al., filed on Dec. 24, 2011
[0082]Emission from a VCSEL device is generally (although not always) a Gaussian like narrow beam in the sense that most of the beam's energy is located at the center of its transverse distribution. In many applications and in particular, in an illuminator application it is often desired to shape the output beam of a VCSEL device. The applicants in the co-authored and co-owned pending U.S. patent application Ser. No. 13/337,098 by Seurin et al., filed on Dec. 24, 2011 disclosed different methods to shape VCSEL output beams. That description is being incorporated by reference in its entirety. FIG. 7 shows a few exemplary embodiments of beam shaping methods that may be used in conjunction with the array modules described in reference with FIGS. 4, 5 and 6. Each element shown in embodiments 7a, 7b and 7c are labeled using substantially similar reference numerals as in FIGS. 4, 5 and 6. The elements represented by similar reference numerals will therefore not be described in detail again.
[0083]More specifically, the embodiment shown in FIG. 7a comprises an array chip section 700 and carrier substrate section 710. The array chip section is substantially similar to the one described in reference with FIG. 4a. That description will not be repeated. The carrier substrate 710 comprises a substrate 711 having one side coated with an antireflection layer 712. Furthermore, a metallization layer 714 having windows aligned with the chip array windows 708 is disposed on the antireflection layer proximal to the array chip. The remaining contiguous metallization layer surrounding the windows forming metal pads are used to bond the sections 710 and 700. Unlike the optical array described in reference with FIG. 4a, the top emission surface of the substrate section is constructed to have an optical element for beam shaping, for example a diffuser 715 instead of a second antireflection layer (414 in FIG. 4a). As a result, the light 709 emitted out of the array module is diffused.
[0084]In some other applications, in addition to reducing speckle for example, the diffuser is also used to increase the divergence angle of the array to a predetermined number. The embodiment shown in FIG. 7a is particularly suitable for an application where a uniform diffused illumination pattern is preferred for example, security illumination for perimeter monitoring, where cameras of certain field of view are used with laser illuminators illuminating the same field of view, or illumination for 3D imaging or gesture recognition, where illumination of a rectangular field of view of certain divergence angle, matching the camera divergence is required. In addition, 715 may be a diffractive or holographic optical element, for example.
[0085]Although the divergence angle of a VCSEL emission is quite small (˜10-15°), output from a VCSEL still spreads over a large distance away from the emission surface. As a consequence, the light emitted from the module may not be focused uniformly over a large surface area at a large distance from the illumination surface. In another embodiment of the invention shown in FIG. 7b having an array chip 700 and a transparent carrier substrate section 711, the top emission surface of the carrier substrate section includes an additional optical element, for example an array of microlenses 716, each microlens in the array is aligned with a corresponding emission window 708 on the array chip. One advantage of having individual microlenses is to collimate and reduce the angle of the diverging beam, for example.
[0086]The height at which microlenses are disposed above the array chip may be pre-determined and precisely controlled by the thickness of the carrier substrate 711 for example, such that individual emissions from adjacent VCSELs each collimated using a corresponding microlens, fill up the dark space between the adjacent emissions. As a result, overall emission from the entire array module is distributed uniformly even at considerably large distance away from the array module. This embodiment may be particularly suitable for an application where an array module is configured to pump a solid state gain medium as described earlier in the co-authored (by some of the applicants) and co-owned U.S. patent application Ser. No. 13/369,581 filed on Feb. 9, 2012, by van Leeuwen et al. now issued as the U.S. Pat. No. 8,576,885 on Nov. 5, 2013.
[0087]In an alternative embodiment shown in FIG. 7c, which is otherwise identical to the array module described in reference with FIG. 4a, an additional optical element including a carrier substrate 720 having an array of micro-lenses 726 is disposed above the carrier substrate 711 and the array module 700. The microlens array is positioned at a predetermined height where each microlens in the array is aligned with an emission window 708. One advantage of this embodiment is that a prefabricated microlens array may be added or bonded to an existing array module similar to that shown in FIG. 4a, for example.
[0088]In general, a carrier substrate may include but is not limited to, glass, sapphire, diamond, etc. Although the principles of this embodiment is described in reference with a top emitting array module, other types of array modules described in other embodiments are not precluded. Furthermore, the basic idea of having additional optical elements is conveyed using a few representative examples. It should not be construed that other types of optical elements suitable for beam shaping are precluded.
[0089]In an alternative embodiment, larger size array modules are produced by configuring a plurality of array chips electrically connected in predetermined arrangement for different applications, as shown in FIGS. 8a and 8b. The plurality of array chips may be connected in a wafer level processing, as well as by assembling them on a common transparent carrier substrate. Although FIGS. 8a and 8b show a plurality of array chips, for clarity of representation, only one set of elements are labeled. Furthermore, identical elements or elements with similar functionalities in FIGS. 8a and 8b are labeled with same reference numerals unless stated otherwise. To keep the description short, identical elements in FIGS. 8a and 8b will be described together and only the differences between the two embodiments will be described separately.
[0090]More specifically, the array modules shown in FIGS. 8a and 8b include a plurality of surface mountable array chips 800 substantially similar to the ones described in reference with FIGS. 2a, 2b, 2c and 2d. The surface mountable array chips will not be described in detail. The array chips may be electrically connected at the wafer level (or assembled) in a predetermined pattern on a common trans